september 2016 docid027065 rev 4 1 / 8 for further information contact your local stmicroelectronics sales office www.st.com steval - ih p007v1 power line communication module for street lighting data brief features ? sm6t15ca: transil 600 w tvs diode ? smaj5.0ca - tr: transil 400 w tvs diode ? st7580: fsk, psk multi - mode power line networking system - on - chip ? stm32f103cbt7: stm32 arm - based 32 - bit mcu ? stps1l30: low drop power schottky rectifier 1 a, 30 v, 0.3 v ? stth1l06a: turbo 2 ultrafast high voltage rectifier ? rohs compliant description the steval - ihp007v1 evaluation board is a power line communication module addition to the steval - ilh007v1 hid ballast module. it provides functions for the management of street lighting network architectu re in the cenelec a - b - d bands. the module is based on an stm32f103cbt7 arm cortex - m3 microcontroller and an st7580 psk narrow band power line modem with up to 28.8 kbps data rate. the embedded mcu can be easily replaced with an equivalent 48 - pin mcu from t he stm32f0, stm32f2, stm32f3 families with a few changes. the module is designed to work with the steval - ilh007v1 hid module, but can be associated with other lighting driver boards with a standard serial communication port. note that this board only funct ions in a network with an evalkitst7580 - 1 board designated as the master; this is achieved via uart commands.
schematic diagrams steval - ihp007v1 2 / 8 docid027065 rev 4 schematic diagrams figure 1 : steval - ihp007v1 circuit schematic (1 of 5) vfqf p n4 8 e p 4 9 t xd 1 rx d 2 3 vddi o 4 t rs t n 5 t m s 6 g n d t c k 7 8 t do 9 t d i re s e t n 1 0 vd d 1 1 xi n 1 2 1 3 x g v v s o n d s u d d a _ t p l l v z c c _ c i a n r x _ i n tx _ ou t p a _ i n + p a _ i n - c v l c c vs s p a _ ou t 2 5 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 vvd _ r e p l _ s r e e g _ vdd i vdd i v s g 1 rve d s n d n c n c n c v 8 o o a 2 3 3 2 3 3 3 2 2 8 4 1 9 0 2 3 6 7 cl _ s e l 3 3 6 5 r x _ o n 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 t_ r b b r r e q 1 0 u 2 s t 758 0 r r r r r e e e e e p l _ s e s e s e s e s e t r r r r r x v v v v v g v _ e e e e e n d o d d d d d n d d 1 2 3 4 5 4 8 l e d s md l d 1 h s mf - c1 5 5 060 3 r 4 560 r 060 3 r 6 560 r vddi o br 0 br 1 ca t 16 - j 4 1 2 3 4 8 7 6 5 rp 1 4 x 10 k vddi o p l c _ rx d p l c_ t x d 040 2 c 4 vddi o 100n 16 v 8 m h z_ m c o 040 2 c1 0 100n 16 v l 2 080 5 b l m 21p g 331s n 1 c1 6 4u7 16 v g nd_ a g nd_ a 040 2 c1 9 100n 16 v g nd_ a 040 2 c1 7 100 p 25 v g nd_ a 040 2 c2 4 100n 16 v g nd_ a 080 5 c2 1 10u 16 v g nd_ a vcc_ a vdd_ p l l 040 2 c2 0 100n 16 v 080 5 c1 8 10u 16 v zc_ i n r x _ i n tx _ ou t p a _ i n + c l p a _ i n - vc c 040 2 c2 2 100 p 25 v 040 2 r1 5 130 r 040 2 r1 6 330 r 1 2 3 q 1 2 n7 00 2 040 2 r1 7 10 k vddi o cl _ s e l cl _ s e l g nd_ a 080 5 l 1 b l m2 1 pg 300 s n 1 p l _ rx _ o n p l _ tx _ o n p a _ ou t vd d 040 2 r1 0 10 k vddi o p l c _ re s e t n 040 2 c1 2 100n 16 v 080 5 c1 1 10u 16 v vdd _ re g _ 1 v 8 040 2 c 7 080 5 100n 16 v c 8 10u 16 v vddi o 040 2 c 2 100n 16 v g nd_ a vddi o current limit setting ca t 16 - j 4 1 2 3 4 8 7 6 5 rp 2 4 x 10 k 040 2 c 1 100n 16 v 040 2 r 2 10 k vddi o vddi o 040 2 r 9 10 k 040 2 r 8 10 k vddi o transceiver module 040 2 r 3 0 r 040 2 r 1 0 r t_ r e q 040 2 r3 8 10 k vddi o
steval - ihp007v1 schematic diagrams docid027065 rev 4 3 / 8 figure 2 : steval - ihp007v1 circuit schematic (2 of 5) figure 3 : steval - ihp007v1 circuit schematic (3 of 5) 040 2 c2 9 100n 16 v 120 6 r1 8 33 k 120 6 r2 5 33 k 120 6 r2 6 33 k s ot 2 3 q 2 bc8 4 7 040 2 r1 9 22 k 040 2 r3 2 10 m 1 2 4 3 u 3 040 2 hcp l - 181 - 000 e r3 0 33 k vcc_ a vcc_ a z c_ i n g nd_ a g nd_ a l n is olated zero crossing do- 214 a c d 1 s t th 1 l0 6 a 080 5 r2 2 100 k 1 t p 1 z c_ i n boot 0 7 4 4 nrst 5 6 os c _ i n/ p d 0 os c _ out/ p d 1 p a 0 - w k u p 1 1 0 1 p a 9 3 1 p a 1 0 3 2 p a 1 1 3 3 p a 1 2 3 4 p a 1 3 /j t m s /s w di o 3 7 p a 1 5 /j t d i p a 1 1 2 p a 1 4 /j t ck / s w c l k 3 8 p a 2 1 3 p a 3 1 4 p a 4 1 5 p a 5 1 6 p a 7 p a 6 1 7 p a 8 2 3 9 0 2 3 1 1 0 9 8 9 p p p b 0 b 1 b 2 /boot 1 4 0 p b 3 /j t d o p b 4 /jn t rs t p b 5 4 1 p b 6 4 2 p b 7 4 3 2 3 4 6 vdd_ 1 4 8 vdd_ 2 9 vdd_ 3 vdd a vs s _ 1 2 3 3 5 vs s _ 2 4 7 vs s a vs s _ 3 8 p b 8 4 5 p b 9 4 6 p b1 0 2 1 p b1 1 2 2 p b1 2 2 5 p b1 3 2 6 p b1 4 2 7 p b1 5 2 8 1 vba t p c1 3 /t a mp e r_ r t c 2 3 u 1 p c1 5 /o s c3 2 _ ou t p c1 4 /o s c3 2_ i n 4 i c- s tm3 2 f 10 3 cbt 7 x 2 040 2 f ox s dlf/ 080 - 2 0 c 5 22 p 50 v 040 2 c 9 22 p 50 v vddi o p l _ rx _ o n p l _ tx _ o n p l c _ re s e t n j ta g _ td o j ta g _ tr s t j ta g _ tc k j ta g _ td i j ta g _ tm s os c 32_ i n os c 32 _ ou t 040 2 c1 5 100n 16 v 060 3 l 3 vdd a 080 5 b l m1 8 a g 102 s n1 d c1 4 vddi o 10u 16 v bt 1 cr2 032 / 1 h f vba t 040 2 r 5 330 r p l c _ rx d p l c_ t x d t _ re q p l m_ g p i o 0 p l m_ g p i o 1 p l m_ g p i o 2 p l m_ g p i o 3 p l m_ g p i o 4 p l m_ g p i o 5 p l m_ g p i o 6 boot 1 p l m_ g p i o 7 8 mhz _ mc o us a rt_ t x us a rt_ r x s t m3 2 _ u s b _ dm s t m3 2 _ u s b _ d p s p i _ mos i s p i _ mi s o s p i _ s c k boot 0 s p i _ ns s 040 2 r1 3 10 k 040 2 c1 3 100n 16 v 040 2 r1 2 10 k vddi o 040 2 r1 1 1 m h ost controller x 1 mc- 30 6 040 2 c 3 10 p 50 v 040 2 c 6 10 p 50 v 040 2 c3 7 100n 16 v 080 5 c2 3 10u 16 v 040 2 c3 8 100n 16 v vddi o 040 2 c3 9 100n 16 v 040 2 r1 4 10 k vddi o re s e t_ u p ( u p tx ) ( u p rx ) vddi o 060 3 r3 9 560 r 060 3 r4 0 560 r l e d s md l d 2 h s mf - c1 5 5 l e d _ re d l e d_ g r ee n
schematic diagrams steval - ihp007v1 4 / 8 docid027065 rev 4 figure 4 : steval - ihp007v1 circuit schematic (4 of 5) figure 5 : steval - ihp007v1 circuit schematic (5 of 5) 1 8 x 8 x 1 6 c 3 2 220 n x 2 2 5 0 v a c l 4 1 4 10 u 2 . 0 a 8 5 1 : 1 z t 1 s m b d 4 t 6040 3 - k 502 4 - x 0 4 4 s m 6 t 1 5 c a 06 0 3 r 3 4 15 0 r d o 2 1 4 d 5 s m a j 5 . 0 c a 06 0 3 c 3 6 s m d 18 n 5 0 v l 5 100 u 3 5 0 m a 06 0 3 c 3 5 10 n 5 0 v 12 1 0 c 3 0 10 u 5 0 v d 3 d o - 21 4 a c ( s m a ) s t p s 1 l 3 0 a d 2 d o - 21 4 a c ( s m a ) v c c s t p s 1 l 3 0 a 04 0 2 r 2 3 2 4 k 04 0 2 r 3 1 2 4 k v c c p a _ o u t 04 0 2 r 2 1 3 3 k p a p a _ i n + p a _ i n - 04 0 2 r 2 0 1 0 k 04 0 2 c 2 8 100 n 1 6 v 04 0 2 r 2 9 2 2 k 04 0 2 c 3 4 10 0 p 2 5 v 04 0 2 r 2 8 5 k 1 04 0 2 r 2 7 1 k 5 04 0 2 c 2 5 10 0 p 2 5 v 04 0 2 c 2 6 2 7 p 5 0 v 04 0 2 c 2 7 4 . 7 p 5 0 v 04 0 2 c 3 3 1 n 5 0 v 04 0 2 r 2 4 4 7 k 04 0 2 r 3 3 4 7 k 04 0 2 c 3 1 v c c 100 n 1 6 v t x _ o u t l n c o m m 1 2 3 power line coupling section 4 5 j 2 l n c o m m 9012 1 - 07 6 5 r x _ i n 1 t p 2 t x _ o u t 1 t p 3 r x _ i n j 1 1 2 3 4 5 6 7 8 90120 - 076 8 c a t 16 - j 4 1 2 3 4 8 7 6 5 rp 3 4 x 10 k 040 2 r 7 10 k j ta g _ tc k j ta g _ t d i j ta g _ td o j ta g _ tm s j ta g _ tr s t re s e t_ u p vddi o jt a g interface
steval - ihp007v1 steval - ihp007v1 firmware section docid027065 rev 4 5 / 8 steval - ihp007v1 firmware section figure 6 : firmware architecture figure 7 : data link architecture
steval - ihp007v1 firmware section steval - ihp007v1 6 / 8 docid027065 rev 4 figure 8 : application architecture
steval - ihp007v1 revision history docid027065 rev 4 7 / 8 revision history table 1: document revision history date rev changes 09 - feb - 2015 1 first release. 23 - jul - 2015 2 description has been updated. 07 - jan - 2016 3 updated board photo on the cover page. 02 - sep - 2016 4 text and formatting changes throughout document. updated cover page description. updated figure 6: "firmware architecture"
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